A New High-Performance Digital FM Modulator and Demodulator for Software-Defined Radio and Its FPGA Implementation

Table 6

FPGA resource usage comparison result with other FM demodulators.

Architecture using Xilinx Spartan3 3S200FT256-4	Time		Area
	Delay (ns)	Frequency (MHz)	Slices	Slices FF	LUT
PLL (optimized) [7]	9.725	102.828	491	548	721
Sigma Delta Arch. [11]	2427 out of 3071 slices in Xilinx Virtex2 XC2V500 device
Proposed implementation	12.948	77.3	237	244	437
	234 out of 3072 slices in Xilinx Virtex2 XC2V500 device