Research Article
Sustainable Modular Adaptive Redundancy Technique Emphasizing Partial Reconfiguration for Reduced Power Consumption
Table 3
System modules implementation.
| Module | Implementation platform |
| Organic layer | ML402 (lower board of VSK) with Virtex-4 FPGA (XCV4SX35) | Video capturing/buffering | Video IO Daughter Card (VIODC) (Upper board of VSK) with Virtex-2 PRO FPGA (XCV2P7) | HW-SW connection | JTAG-GNAT from FPGA sideXilinx Parallel port from PC side | Communication Class | Multithreaded C++ application | HIM | C++ Message encoder/decoder | GUI monitor | Java applet | Application | Sobel edge detector (Verilog) | OGA engine | C++ based Standard GA [21] | OGA interface | C-based API (MRRA) [23] |
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