A High-Speed Dynamic Partial Reconfiguration Controller Using Direct Memory Access Through a Multiport Memory Controller and Overclocking with Active Feedback

Table 2

HSDPRC write and read throughput. A DMA controller is used during dynamic partial reconfiguration. An interrupt is used to signal completion. Despite the fact that they share the same ICAP frequency of 100 MHz with previous devices (Virex-II and Virtex-4), the Virtex-5 results can be further improved to run at the maximum possible speed as described in Section 5.2.

Platform	Processor, System Freq	Memory Controller	TX; Freq	RX; Freq
ML410; (Virtex 4)	PowerPC 405, 200 MHz	MPMC	177.4 MB/s @100 MHz	180.0 MB/s @100 MHz
ML507; (Virtex 5)	MicroBlaze, 200 MHz	MPMC	178.6 MB/s @100 MHz	181.0 MB/s @100 MHz
ML507; (Virtex 5)	PowerPC 440, 200 MHz	PPC440MC	335.9 MB/s @100 MHz	340.4 MB/s @100 MHz
ML507; (Virtex 5)	PowerPC 440, 266 MHz	PPC440MC	418.5 MB/s @133 MHz	424.6 MB/s @133 MHz