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International Journal of Reconfigurable Computing
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International Journal of Reconfigurable Computing
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2011
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Article
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Tab 3
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Research Article
A High-Speed Dynamic Partial Reconfiguration Controller Using Direct Memory Access Through a Multiport Memory Controller and Overclocking with Active Feedback
Table 3
HSDPRC device utilization for Virtex-5.
Virtex-5 device utilization for HSDPRC.
Number of ICAPs
1
Number of RAMB18X2SDPs
1
Number of slice registers
1085
Number used as flip flops
1082
Number used as Latches
3
Number of slice LUTS
923
Number of slice LUT-flip
1530
Flop pairs