The Potential for a GPU-Like Overlay Architecture for FPGAs

<table class="table-group" width="800px"><tr class="fig-image" id="a"><td><img alt="514581.fig.0012a" src="https://static.hindawi.com/articles/ijrc/volume-2011/514581/figures/514581.fig.0012a.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(a) </b>8-bit HT interface</td></tr></table></td></tr><tr class="fig-image" id="b"><td><img alt="514581.fig.0012b" src="https://static.hindawi.com/articles/ijrc/volume-2011/514581/figures/514581.fig.0012b.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(b) </b>16-bit HT interface</td></tr></table></td></tr></table>

<table>Speedup versus a single hardware batch context for (a) 8-bit and (b) 16-bit HT interfaces.</table>

International Journal of Reconfigurable Computing

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Figure 12

Figure 12: The Potential for a GPU-Like Overlay Architecture for FPGAs 