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International Journal of Reconfigurable Computing
Volume 2011 (2011), Article ID 518602, 19 pages
Research Article

A Dynamic Dual Fixed-Point Arithmetic Architecture for FPGAs

1Department of Electrical and Computer Engineering, The University of New Mexico, Albuquerque, NM 87101, USA
2Space Electronics Branch of the Space Vehicles, Directorate of the Air Force Research Laboratory, NM 87117-5776, USA

Received 17 July 2010; Revised 30 November 2010; Accepted 18 January 2011

Academic Editor: Scott Hauck

Copyright © 2011 G. Alonzo Vera et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

G. Alonzo Vera, Marios Pattichis, and James Lyke, “A Dynamic Dual Fixed-Point Arithmetic Architecture for FPGAs,” International Journal of Reconfigurable Computing, vol. 2011, Article ID 518602, 19 pages, 2011. doi:10.1155/2011/518602