A Dynamic Dual Fixed-Point Arithmetic Architecture for FPGAs

Figure 4

Dual fixed-point adder’s block diagram. The three stages of the adder are depicted by the dashed lines. Expressions like 𝑎₀≫𝑛₀ represent an arithmetical shift (with sign extension) to the right of 𝑛₀ bits for the operand 𝑎_𝑜. The components that need to be reconfigured to enable a change in precision in a dynamic dual fixed-point adder are shown in gray.