A Dynamic Dual Fixed-Point Arithmetic Architecture for FPGAs

Table 2

Implementation results for Virtex 4 (XC4VFX12) using ISE 9.2.4i with default settings.

	FX (32_24)	DDFX (32_24_4)	SFPU
Addition
Equiv. gates	1421	3508	11297
Max. freq.	≈302 MHz	≈309 MHz	≈270 MHz
Multiplication
Equiv. gates	23290	16497	14896
Max. freq.	≈219.6 MHz	≈250.8 MHz	≈248.9 MHz