Evaluation of the Reconfiguration of the Data Acquisition System for 3D USCT

<table>Passive serial configuration of the FPGAs on an FLC at system startup time: firstly, the control FPGA and after that the computing FPGAs are configured in parallel with configuration data from an embedded ROM.</table>

International Journal of Reconfigurable Computing

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Figure 6

Figure 6: Evaluation of the Reconfiguration of the Data Acquisition System for 3D USCT 