Evaluation of the Reconfiguration of the Data Acquisition System for 3D USCT

<table>Communication structure during processing mode on an FLC: bidirectional data transfer is only possible via the slower Local Bus (80 MB/s). Separate point-to-point links (<i>chip_select</i> &amp; <i>busy</i>) are used for control and synchronization of parallel processes. A further single point-to-point link is connected to all four FPGAs, indicating the current system state, that is, DAQ or processing mode.</table>

International Journal of Reconfigurable Computing

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Figure 8

Figure 8: Evaluation of the Reconfiguration of the Data Acquisition System for 3D USCT 