Evaluation of the Reconfiguration of the Data Acquisition System for 3D USCT

<table>Block diagram of a computing FPGA: generic interfaces for communication with the control FPGA (communication I/F) via Local Bus or Fast Links and access to QDRII memory (memory I/F). The variable algorithmic part is also indicated.</table>

International Journal of Reconfigurable Computing

fig9

Figure 9

Figure 9: Evaluation of the Reconfiguration of the Data Acquisition System for 3D USCT 