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International Journal of Reconfigurable Computing
Volume 2012 (2012), Article ID 127302, 10 pages
http://dx.doi.org/10.1155/2012/127302
Research Article

Using Partial Reconfiguration and Message Passing to Enable FPGA-Based Generic Computing Platforms

1ArchES Computing Systems, 708-222 Spadina Avenue, Toronto, ON, Canada M5T 3A2
2The Edward S. Rogers Sr. Department of Electrical and Computer Engineering, University of Toronto, 10 King's College Road, Toronto, ON, Canada M5S 3G4

Received 12 May 2011; Accepted 22 August 2011

Academic Editor: Marco D. Santambrogio

Copyright © 2012 Manuel Saldaña et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Linked References

  1. Xilinx, Inc., “Partial Reconfiguration User Guide,” http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_2/ug702.pdf.
  2. M. Saldaña, A. Patel, H. J. Liu, and P. Chow, “Using partial reconfiguration in an embedded message-passing system,” in Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig '10), pp. 418–423, December 2010.
  3. ArchES Computing, Inc., http://www.archescomputing.com.
  4. M. Saldaña, A. Patel, C. Madill et al., “MPI as an abstraction for software-hardware interaction for HPRCs,” in Proceedings of the 2nd International Workshop on High-Performance Reconfigurable Computing Technology and Applications (HPRCTA '08), pp. 1–10, November 2008. View at Publisher · View at Google Scholar · View at Scopus
  5. P. Lysaght, B. Blodget, J. Mason, J. Young, and B. Bridgford, “Invited paper: enhanced architectures, design methodologies and CAD tools for dynamic reconfiguration of Xilinx FPGAS,” in Proceedings of the International Conference on Field Programmable Logic and Applications (FPL '06), pp. 1–6, August 2006. View at Publisher · View at Google Scholar · View at Scopus
  6. O. Diessel, H. ElGindy, M. Middendorf, H. Schmeck, and B. Schmidt, “Dynamic scheduling of tasks on partially reconfigurable FPGAs,” IEE Proceedings: Computers and Digital Techniques, vol. 147, no. 3, pp. 181–188, 2000. View at Publisher · View at Google Scholar · View at Scopus
  7. C. Bobda, A. Ahmadinia, M. Majer, J. Teich, S. Fekete, and J. van der Veen, “DyNoC: a dynamic infrastructure for communication in dynamically reconfigurable devices,” in Proceedings of the International Conference on Field Programmable Logic and Applications (FPL '05), pp. 153–158, August 2005. View at Publisher · View at Google Scholar · View at Scopus
  8. K. Papadimitriou, A. Anyfantis, and A. Dollas, “An effective framework to evaluate dynamic partial reconfiguration in FPGA systems,” IEEE Transactions on Instrumentation and Measurement, vol. 59, no. 6, pp. 1642–1651, 2010. View at Publisher · View at Google Scholar · View at Scopus
  9. C. Rossmeissl, A. Sreeramareddy, and A. Akoglu, “Partial bitstream 2-D core relocation for reconfigurable architectures,” in Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems (AHS '09), pp. 98–105, August 2009. View at Publisher · View at Google Scholar · View at Scopus
  10. H. Kalte and M. Porrmann, “Context saving and restoring for multitasking in reconfigurable systems,” in Proceedings of the International Conference on Field Programmable Logic and Applications (FPL '05), pp. 223–228, August 2005. View at Publisher · View at Google Scholar · View at Scopus
  11. D. Koch and J. Teich, “Platform-independent methodology for partial reconfiguration,” in Proceedings of the 1st Conference on Computing Frontiers (CF '04), pp. 398–403, ACM, New York, NY, USA, 2004. View at Publisher · View at Google Scholar
  12. H.-H. So, A. Tkachenko, and R. Brodersen, “A unified hardware/software runtime environment for FPGA-based reconfigurable computers using BORPH,” in Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06), pp. 259–264, October 2006. View at Publisher · View at Google Scholar · View at Scopus
  13. L. Möller, R. Soares, E. Carvalho, I. Grehs, N. Calazans, and F. Moraes, “Infrastructure for dynamic reconfigurable systems: choices and trade-offs,” in Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design (SBCCI '06), pp. 44–49, ACM, New York, NY, USA, 2006. View at Publisher · View at Google Scholar
  14. The MPI Forum, “MPI: a message passing interface,” in Proceedings of the ACM/IEEE Conference on Supercomputing, pp. 878–883, ACM, New York, NY, USA, November 1993. View at Scopus
  15. Nallatech, http://www.nallatech.com/.
  16. P. S. Pacheco, Parallel Programming with MPI, Morgan Kaufmann, 1997.
  17. Impulse Accelerated Technologies, http://www.impulseaccelerated.com/.
  18. A. W. House, M. Saldaña, and P. Chow, “Integrating high-level synthesis into MPI,” in Proceedings of the 18th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM '10), pp. 175–178, May 2010. View at Publisher · View at Google Scholar · View at Scopus
  19. M. Saldaña, D. Nunes, E. Ramalho, and P. Chow, “Configuration and programming of heterogeneous multiprocessors on a multi-FPGA system using TMD-MPI,” in Proceedings of the IEEE International Conference on Reconfigurable Computing and FPGA's, (ReConFig '06), pp. 1–10, September 2006. View at Publisher · View at Google Scholar · View at Scopus
  20. G. Bradski, “The OpenCV Library,” Dr. Dobb's Journal of Software Tools, 2000. View at Google Scholar