Research Article
Novel Dynamic Partial Reconfiguration Implementation of K-Means Clustering on FPGAs: Comparative Results with GPPs and GPUs
Table 2
Implementation results.
| Compare | Xilinx XCV1000 [4] | Xilinx XC4VFX12 |
| Slices | 8884/12288 | 5107/5549 | LUTs | 17768 | 10216 | Max. clock frequency | 63.07 MHz | 100 MHz | Single loop processing time | 0.17 s | ~0.07 s |
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