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International Journal of Reconfigurable Computing
Volume 2012, Article ID 163542, 17 pages
Research Article

A Coarse-Grained Reconfigurable Architecture with Compilation for High Performance

1ECE Illinois, University of Illinois at Urbana-Champaign, Urbana, IL 61801-2918, USA
2Magma Design Automation, Inc., San Jose, CA 95110, USA

Received 5 October 2011; Revised 5 January 2012; Accepted 9 January 2012

Academic Editor: Kentaro Sano

Copyright © 2012 Lu Wan et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


We propose a fast data relay (FDR) mechanism to enhance existing CGRA (coarse-grained reconfigurable architecture). FDR can not only provide multicycle data transmission in concurrent with computations but also convert resource-demanding inter-processing-element global data accesses into local data accesses to avoid communication congestion. We also propose the supporting compiler techniques that can efficiently utilize the FDR feature to achieve higher performance for a variety of applications. Our results on FDR-based CGRA are compared with two other works in this field: ADRES and RCP. Experimental results for various multimedia applications show that FDR combined with the new compiler deliver up to 29% and 21% higher performance than ADRES and RCP, respectively.