Research Article
DMPDS: A Fast Motion Estimation Algorithm Targeting High Resolution Videos and Its FPGA Implementation
Table 4
Synthesis results and comparisons.
| Architecture | Technology | Frequency (MHz) | Area | Memory (K bits) | Cycles per block | 1080 p fps | QFHD fps |
|
Porto et al. [6] | Stratix 4 | 199.2 | 34.5 KALUTS | 46.2 | 170 | 144 | 36 |
Kao et al. [14] | 180 nm | 154 | 321 KGates | 9.72 | 631 | 30 | 7.5 |
Tasdizen et al. [15] | Virtex 5 | 130 | 2282 KCLBs | 0.51 | 467 | 34 | 8.5 |
Vanne et al. [16] | 130 nm | 200 | 14 KGates | 2.5 | 390/437/680 | 63/56/36 | 15.75/14/9 |
Lai et al. [17] | 180 nm | 83.3 | 26 KGates | 28.7 | 1282 | 8 | 2 |
Yin et al. [18] | 180 nm | 200 | 260 KGates | 11.3 | 872 | 28 | 7 |
Cetin and Hamzaoglu [19] | 90 nm FPGA | 63 | 33 KLUTS | 8 dual-port block RAM | 104 (average) | 74.7 | 18.7 | DMPDS | Stratix 4 | 187.58 | 34.5 KALUTs | 46.2 | 170 | 136 | 34 | DMPDS | Virtex 5 | 294 | 56.3 KLUTs | — | 170 | 213.2 | 53.3 |
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