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International Journal of Reconfigurable Computing
Volume 2012, Article ID 219717, 10 pages
http://dx.doi.org/10.1155/2012/219717
Research Article

Exploration of Uninitialized Configuration Memory Space for Intrinsic Identification of Xilinx Virtex-5 FPGA Devices

Institute for Information Processing Technology (ITIV), Karlsruhe Institute of Technology (KIT), Engesserstr. 5, 76131 Karlsruhe, Germany

Received 8 June 2011; Revised 25 October 2011; Accepted 25 October 2011

Academic Editor: Claudia Feregrino

Copyright © 2012 Oliver Sander et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Linked References

  1. B. Gassend, D. Clarke, M. van Dijk, and S. Devadas, “Silicon physical random functions,” in Proceedings of the 9th ACM Conference on Computer and Communications Security (CCS '02), pp. 148–160, ACM, New York, NY, USA, November 2002. View at Scopus
  2. B. Gassend, D. Lim, D. Clarke, M. van Dijk, and S. Devadas, “Identification and authentication of integrated circuits,” Concurrency and Computation: Practice and Experience, vol. 16, no. 11, pp. 1077–1098, 2004. View at Google Scholar
  3. J. Guajardo, S. S. Kumar, G.-J. Schrijen, and P. Tuyls, “Fpga intrinsic pufs and their use for ip protection,” in Proceedings of the 9th International Workshop on Cryptographic Hardware and Embedded Systems (CHES ’07), pp. 63–80, Springer, Berlin, Germany, 2007.
  4. P. Tuyls and B. Skoric, “Strong authentication with physical unclonable functions,” in Security, Privacy, and Trust in Modern Data Management, M. Petkovic and W. Jonker, Eds., Data-Centric Systems and Applications, pp. 133–148, Springer, Berlin, Germany, 2007. View at Publisher · View at Google Scholar
  5. R. Maes, “PUF Bibliography,” 2010, http://www.rmaes.ulyssis.be/pufbib.php/.
  6. R. Maes, P. Tuyls, and I. Verbauwhede, “Intrinsic pufs from flip-flops on reconfigurable devices,” in Proceedings of the 3rd Benelux Workshop on Information and System Security (WISSec '08), p. 17, Eindhoven, NL, USA, 2008.
  7. S. S. Kumar, J. Guajardo, R. Maes, G. J. Schrijen, and P. Tuyls, “The butterfly PUF protecting IP on every FPGA,” in Proceedings of the IEEE International Workshop on Hardware-Oriented Security and Trust (HOST '08), pp. 67–70, June 2008. View at Publisher · View at Google Scholar · View at Scopus
  8. Y. Su, J. Holleman, and B. Otis, “A1.6pJ/blt 96% stable chip-ID generating circuit using process variations,” in Proceedings of the 54th IEEE International Solid-State Circuits Conference (ISSCC '07), pp. 406–611, San Francisco, Calif, USA, February 2007. View at Publisher · View at Google Scholar · View at Scopus
  9. D. E. Holcomb, W. P. Burleson, and K. Fu, “Power-up SRAM state as an identifying fingerprint and source of true random numbers,” IEEE Transactions on Computers, vol. 58, no. 9, pp. 1198–1210, 2009. View at Publisher · View at Google Scholar · View at Scopus
  10. S. Chaudhry, P. A. Layman, J. G. Norman, and J. R. Thomson, “Electronic fingerprinting of semiconductor integrated circuits,” US patent 6,738,294, Agere Systems Inc., 2002.
  11. Y. Dodis, R. Ostrovsky, L. Reyzin, and A. Smith, “Fuzzy extractors: how to generate strong keys from biometrics and other noisy data,” SIAM Journal on Computing, vol. 38, no. 1, pp. 97–139, 2008. View at Publisher · View at Google Scholar · View at Scopus
  12. O. Sander, B. Glas, L. Braun, K. Müller-Glaser, and J. Becker, “Intrinsic identification of xilinx virtex-5 fpga devices using uninitialized parts of configuration memory space,” in International Conference on Reconfigurable Computing and FPGAs (ReConFig '10), pp. 13–18, December 2010.
  13. Xilinx Inc., UG190: Virtex-5 FPGA User Guide, 2009, v5.2, November 2009.
  14. Xilinx Inc., UG191: Virtex-5 FPGA Configuration User Guide, 2009, v3.8, 14.08.2009.
  15. IEEE, “1149.1: IEEE Standard Test Access Port and Boundary-Scan Architecture,” IEEE-SA Standards Board, IEEE Standard 1149.1-2001 (R2008), 2006.
  16. Digilent Inc., DPCUTIL Programmer’s Reference Manual, 2007, doc 576-000, August 2007, http://www.digilentinc.com/Data/Software/Adept/DPCUTIL_Programmers_RM.pdf.
  17. Xilinx Inc., DS100: Virtex-5 Family Overview. Product Specification, 2009, v5.0, February 2009.
  18. Xilinx Inc., UG347: ML505/ML506/ML507 Evaluation Platform: User Guide, 2009, v3.1.1, October 2009.