International Journal of Reconfigurable Computing / 2012 / Article / Tab 2

Research Article

Configurable Transmitter and Systolic Channel Estimator Architectures for Data-Dependent Superimposed Training Communications Systems

Table 2

Synthesis results of the SYSDCE.

Input length (without CP)( )512
Frequency(MHz)115.247
Slice registers(69120)1370 (1%)
Slice LUTs(69120)2587 (3%)
Fully used LUT-FF pairs(3348)609 (18%)
Block RAMs(148)8 (5%)
DSP48Es(64)32 (50%)