International Journal of Reconfigurable Computing / 2012 / Article / Tab 3

Research Article

Configurable Transmitter and Systolic Channel Estimator Architectures for Data-Dependent Superimposed Training Communications Systems

Table 3

Channel estimator throughputs comparison.

Channel estimatorInput lengthCycles/estimation
CT (us)TP (MS/s)TP/area (MS/s/
slices)

SYSDCE (cyclic mean mode)5125915.128101.40
SYSDCE
(channel estimator mode)
5126065.25898.91
Arithmetic mean coprocessor in [10]51222382026.39NA