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International Journal of Reconfigurable Computing
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International Journal of Reconfigurable Computing
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2012
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Article
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Tab 3
Research Article
Configurable Transmitter and Systolic Channel Estimator Architectures for Data-Dependent Superimposed Training Communications Systems
Table 3
Channel estimator throughputs comparison.
Channel estimator
Input length
Cycles/estimation
CT (us)
TP (MS/s)
TP/area (MS/s/
slices)
SYSDCE (cyclic mean mode)
512
591
5.128
101.40
SYSDCE
(channel estimator mode)
512
606
5.258
98.91
Arithmetic mean coprocessor in [
10
]
512
2238
20
26.39
NA