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International Journal of Reconfigurable Computing
Volume 2012, Article ID 360242, 9 pages
http://dx.doi.org/10.1155/2012/360242
Research Article

Blind Cartography for Side Channel Attacks: Cross-Correlation Cartography

Télécom ParisTech, Institut Télécom CNRS LTCI, 46 rue Barrault, F-75634 Paris Cedex 13, France

Received 12 July 2011; Revised 20 October 2011; Accepted 27 December 2011

Academic Editor: Kris Gaj

Copyright © 2012 Laurent Sauvage et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Linked References

  1. P. C. Kocher, J. Jaffe, and B. Jun, “Differential power analysis,” in Proceedings of the 19th Annual International Cryptology Conference Advances in Cryptology (CRYPTO ’99), vol. 1666 of Lecture Notes in Computer Science, pp. 388–397, Springer, Santa Barbara, Cali, USA, 1999.
  2. R. Anderson and M. Kuhn, “Tamper resistance—a cautionary note,” in Proceedings of the 2nd USENIX Workshop on Electronic Commerce (WOEC’96), pp. 1–11, USENIX Association, Berkeley, Calif, USA, 1996.
  3. K. Gandolfi, C. Mourtel, and F. Olivier, “Electromagnetic analysis: concrete results,” in Proceedings of the 3rd International Workshop Cryptographic Hardware and Embedded Systems (CHES'01), C. K. Koc, D. Naccache, and C. Paar, Eds., vol. 2162 of Lecture Notes in Computer Science, pp. 251–261, Springer, Paris, France, 2001.
  4. M. Agoyan, J.-M. Dutertre, A.-P. Mirbaha, D. Naccache, A.-L. Ribotta, and A. Tria, “Single-bit DFA using multiple-byte laser fault injection,” in Proceedings of the IEEE International Conference on Technologies for Homeland Security (HST'10), pp. 113–119, 2010.
  5. G. Canivet, J. Clédière, J. B. Ferron, F. Valette, M. Renaudin, and R. Leveugle, “Detailed analyses of single laser shot effects in the configuration of a Virtex-II FPGA,” in 14th IEEE International On-Line Testing Symposium, (IOLTS '08), pp. 289–294, Rhodes, Greece, 2008.
  6. S. P. Skorobogatov, “Using optical emission analysis for estimating contribution to power analysis,” in Proceedings of the 6th International Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC '09), pp. 111–119, IEEE Computer Society, Lausanne, Switzerland, 2009.
  7. J. Di-Battista, J.-C. Courrège, B. Rouzeyre, L. Torres, and P. Perdu, “When failure analysis meets side-channel attacks,” in Proceedings of the 12th International Workshop Cryptographic Hardware and Embedded Systems (CHES '10), Santa Barbara, Calif, USA, 2010.
  8. D. Réal, F. Valette, and M. Drissi, “Enhancing correlation electromagnetic attack using planar near-field cartography,” in Proceedings of the Design, Automation and Test in Europe, (DATE '09), pp. 628–633, IEEE, Nice, France, April 2009.
  9. A. Dehbaoui, V. Lomne, P. Maurine, and L. Torres, “Magnitude squared incoherence em analysis for integrated cryptographic module localisation,” Electronics Letters, vol. 45, no. 15, pp. 778–780, 2009. View at Publisher · View at Google Scholar · View at Scopus
  10. L. Sauvage, S. Guilley, and Y. Mathieu, “ElectroMagnetic radiations of FPGAs: high spatial resolution cartography and attack of a cryptographic module,” ACM Transactions on Reconfigurable Technology and Systems, vol. 2, no. 1, pp. 1–24, 2009. View at Google Scholar
  11. L. Sauvage, S. Guilley, J.-L. Danger, Y. Mathieu, and M. Nassar, “Successful attack on an FPGA-based WDDL DES cryptoprocessor without place and route constraints,” in Proceedings of the Design, Automation and Test in Europe (DATE'09), pp. 640–645, IEEE, Nice, France, April, 2009.
  12. É. Brier, C. Clavier, and F. Olivier, “Correlation power analysis with a leakage model,” in Proceedings of the 6th International Workshop Cryptographic Hardware and Embedded Systems (CHES'04), vol. 3156 of Lecture Notes in Computer Science, pp. 16–29, Springer, Cambridge, Mass, USA, August, 2004.
  13. L. Goubin and J. Patarin, “DES and differential power analysis (The “Duplication” Method),” in Proceedings of the 1st International Workshop Cryptographic Hardware and Embedded Systems (CHES’99), vol. 1717 of Lecture Notes in Computer Science, pp. 158–172, Worcester, Mass, USA, August, 1999.
  14. S. Chari, C. S. Jutla, J. R. Rao, and P. Rohatgi, “Towards sound approaches to counteract power-analysis attacks,” in Proceedings of the 19th Annual International Cryptology Conference Advances in Cryptology (CRYPTO ’99), vol. 1666 of Lecture Notes in Computer Science, pp. 398–412, Springer, Santa Barbara, Calif, USA, August, 1999.
  15. J.-L. Danger, S. Guilley, S. Bhasin, and M. Nassar, “Overview of dual rail with precharge logic styles to thwart implementation-level attacks on hardware cryptoprocessors,” in Proceedings of the 3rd International Conference on Signals, Circuits and Systems (SCS'09), pp. 1–8, IEEE, Jerba, Tunisia, November 2009. View at Publisher · View at Google Scholar
  16. National Institute of Standards and Technology, “Data Encryption Standard (DES): FIPS PUB 46-3,” 1999, http://csrc.nist.gov/publications/fips/fips46-3/fips46-3.pdf.
  17. E. Peeters, F.-X. Standaert, N. Donckers, and J.-J. Quisquater, “Improved higher-order side-channel attacks with FPGA experiments,” in Proceedings of the 7th International Workshop Cryptographic Hardware and Embedded Systems (CHES '05), vol. 3659 of Lecture Notes in Computer Science, pp. 309–323, Springer, Edinburgh, UK, 2005.
  18. National Institute of Standards and Technology, “Advanced Encryption Standard (AES): FIPS PUB 197,” 2001, http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf.
  19. T. S. Messerges , “Using second-order power analysis to attack DPA resistant software,” in Proceedings of the 2nd International Workshop Cryptographic Hardware and Embedded Systems (CHES'00), vol. 1965 of Lecture Notes in Computer Science, pp. 238–251, Springer, Worcester, Mass, USA, August, 2000.
  20. “Xilinx FPGA designer,” http://www.xilinx.com/.
  21. “Agilent Technologies,” http://www.home.agilent.com/.
  22. E. Prouff, M. Rivain, and R. Bévan, “Statistical analysis of second order differential power analysis,” IEEE Transactions on Computers, vol. 58, no. 6, pp. 799–811, 2009. View at Publisher · View at Google Scholar · View at Scopus
  23. B. Gierlichs, L. Batina, B. Preneel, and I. Verbauwhede, “Revisiting higher-order DPA attacks: multivariate mutual information analysis,” in Proceedings of the The Cryptographer's Track at RSA Conference (CT-RSA'10), vol. 5985 of Lecture Notes in Computer Science, pp. 221–234, Springer, San Francisco, Calif, USA, March 2010.
  24. E. Prouff, M. Rivain, and R. Bévan, “Statistical analysis of second order differential power analysis,” IEEE Transactions on Computers, vol. 58, no. 6, pp. 799–811, 2009. View at Publisher · View at Google Scholar · View at Scopus
  25. K. Tiri and I. Verbauwhede, “A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation,” in Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE’04), pp. 246–251, IEEE Computer Society, Paris, France, February 2004. View at Publisher · View at Google Scholar
  26. P. Yu and P. Schaumont, “Secure FPGA circuits using controlled placement and routing,” in Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis (CODES+ISSS’07), pp. 45–50, ACM, New York, NY, USA, 2007.
  27. K. Baddam and M. Zwolinski, “Divided Backend duplication methodology for balanced dual rail routing,” in Proceedings of the Cryptographic Hardware and Embedded Systems (CHES '08), vol. 5154 of Lecture Notes in Computer Science, pp. 396–410, Springer, Washington, DC, USA, 2008. View at Publisher · View at Google Scholar
  28. J.-P. Kaps and R. Velegalati , “DPA Resistant AES on FPGA Using Partial DDL,” in Proceedings of the 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machine (FCCM'10), pp. 273–280, IEEE Computer Society, Charlotte, NC, USA, May, 2010. View at Publisher · View at Google Scholar
  29. W. He, E. D. L. Torre, and T. Riesgo , “A precharge-absorbed DPL logic for reducing early propagation effects on FPGA implementations,” in Proceedings of the ReConFig, IEEE Computer Society, Quintana Roo, México, 2011.