On the Feasibility and Limitations of Just-in-Time Instruction Set Extension for FPGA-Based Reconfigurable Processors

Listing 2

IR of candidate found in 5th line of previous listing.

(1) ⋯

(2) %0 = mul float %rdx,    %dx

(3) %1 = mul float %rdy,    %dy

(4) %2 = add float  %0,          %1

(5) %3 = mul float %rdz,    %dz

(6) %4 = add float  %2,          %3

(7) ⋯