International Journal of Reconfigurable Computing / 2012 / Article / Tab 4

Research Article

A Hardware-Accelerated ECDLP with High-Performance Modular Multiplication

Table 4

Comparison with Hardware ECDLP implementations (per core).

Platform
Target curve
Performance (PA/s) Area
(Slices) (BRAMs) (DSPs)

Spartan-3 [16] Binary (130 bit) 111 M 26,731 20 0
Spartan-3 [20] Binary (113 bit) 20 M 13,900 18 0
Spartan-3 [18] Prime (160 bit) 46.80 K 3,230 15 0
Spartan-3 [18] Prime (128 bit) 57.80 K 2,520 16 0
Spartan-3 [19] Prime (160 bit) 50.12 K 2,660 Not given 0
Virtex-5, our system Prime (112 bit) 878 K 5,229 9 130

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