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International Journal of Reconfigurable Computing
Volume 2012, Article ID 439141, 15 pages
http://dx.doi.org/10.1155/2012/439141
Research Article

Exploring Many-Core Design Templates for FPGAs and ASICs

1CSAIL, Massachusetts Institute of Technology, Cambridge, MA 02139, USA
2Department of EECS, University of California at Berkeley, CA 94704, USA

Received 2 May 2011; Accepted 15 July 2011

Academic Editor: Claudia Feregrino

Copyright © 2012 Ilia Lebedev et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

We present a highly productive approach to hardware design based on a many-core microarchitectural template used to implement compute-bound applications expressed in a high-level data-parallel language such as OpenCL. The template is customized on a per-application basis via a range of high-level parameters such as the interconnect topology or processing element architecture. The key benefits of this approach are that it (i) allows programmers to express parallelism through an API defined in a high-level programming language, (ii) supports coarse-grained multithreading and fine-grained threading while permitting bit-level resource control, and (iii) reduces the effort required to repurpose the system for different algorithms or different applications. We compare template-driven design to both full-custom and programmable approaches by studying implementations of a compute-bound data-parallel Bayesian graph inference algorithm across several candidate platforms. Specifically, we examine a range of template-based implementations on both FPGA and ASIC platforms and compare each against full custom designs. Throughout this study, we use a general-purpose graphics processing unit (GPGPU) implementation as a performance and area baseline. We show that our approach, similar in productivity to programmable approaches such as GPGPU applications, yields implementations with performance approaching that of full-custom designs on both FPGA and ASIC platforms.