International Journal of Reconfigurable Computing / 2012 / Article / Alg 1

Research Article

Exploring Many-Core Design Templates for FPGAs and ASICs

Algorithm 1

The reformulated order-graph sampler loop nest. , and are the current {order, graph} scores and graph associated with an order. generates a random order, exchanges nodes in an order, and saves a result for the postprocessing step.
for in    do
end for
for in do
5: for   in   do
  
    Variable initialization:
    
    
10:  end for
  for in do
   for in    do
    
    
15:     
     
   end for
   end for
  for in    do
     Metropolis-hastings:
20:  for in   do
    if
       then
     
     
    end if
25:  end for
   Parallel tempering:
   for in   do
    
    if   then
30:   
   end if
  end for
end for
end for

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