International Journal of Reconfigurable Computing / 2012 / Article / Tab 2

Research Article

Exploring Many-Core Design Templates for FPGAs and ASICs

Table 2

Device die areas and process nodes.

Device Die area (mm2) Process (nm)

Virtex-5 LX155T FPGA 270 65
Nvidia GeForce GTX 580 520 40

We are committed to sharing findings related to COVID-19 as quickly and safely as possible. Any author submitting a COVID-19 paper should notify us at to ensure their research is fast-tracked and made available on a preprint server as soon as possible. We will be providing unlimited waivers of publication charges for accepted articles related to COVID-19. Sign up here as a reviewer to help fast-track new submissions.