International Journal of Reconfigurable Computing / 2012 / Article / Tab 3

Research Article

Exploring Many-Core Design Templates for FPGAs and ASICs

Table 3

Scaled GPGPU design for 65 nm process.

Problem Per-iteration time Scaled per-iteration time
40 nm ( s) 65 nm ( s)

32-Node 21.0 174
37-Node 37.8 312

We are committed to sharing findings related to COVID-19 as quickly and safely as possible. Any author submitting a COVID-19 paper should notify us at to ensure their research is fast-tracked and made available on a preprint server as soon as possible. We will be providing unlimited waivers of publication charges for accepted articles related to COVID-19. Sign up here as a reviewer to help fast-track new submissions.