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International Journal of Reconfigurable Computing
Volume 2012, Article ID 473725, 10 pages
http://dx.doi.org/10.1155/2012/473725
Research Article

A Memory Hierarchy Model Based on Data Reuse for Full-Search Motion Estimation on High-Definition Digital Videos

1Federal Institute of Education, Science and Technology of Rio Grande do Norte, Campus João Câmara, 59550-000 João Câmara, RN, Brazil
2Department of Computer Science and Statistics, Campus Ministro Petronio Portela, Federal University of Piauí, 64049-550 Teresina, PI, Brazil
3Group of Architectures and Integrated Circuits-GACI, Federal University of Pelotas Pelotas, RS, Brazil

Received 20 January 2012; Accepted 19 April 2012

Academic Editor: Alisson Brito

Copyright © 2012 Alba Sandyra Bezerra Lopes et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

The motion estimation is the most complex module in a video encoder requiring a high processing throughput and high memory bandwidth, mainly when the focus is high-definition videos. The throughput problem can be solved increasing the parallelism in the internal operations. The external memory bandwidth may be reduced using a memory hierarchy. This work presents a memory hierarchy model for a full-search motion estimation core. The proposed memory hierarchy model is based on a data reuse scheme considering the full search algorithm features. The proposed memory hierarchy expressively reduces the external memory bandwidth required for the motion estimation process, and it provides a very high data throughput for the ME core. This throughput is necessary to achieve real time when processing high-definition videos. When considering the worst bandwidth scenario, this memory hierarchy is able to reduce the external memory bandwidth in 578 times. A case study for the proposed hierarchy, using search window and block size, was implemented and prototyped on a Virtex 4 FPGA. The results show that it is possible to reach 38 frames per second when processing full HD frames ( pixels) using nearly 299 Mbytes per second of external memory bandwidth.