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International Journal of Reconfigurable Computing
Volume 2012, Article ID 474765, 16 pages
http://dx.doi.org/10.1155/2012/474765
Research Article

Combining SDM-Based Circuit Switching with Packet Switching in a Router for On-Chip Networks

Institute of Information and Communication Technologies, Electronics and Applied Mathematics, Université Catholique de Louvain, 1348 Louvain-la-Neuve, Belgium

Received 1 May 2011; Revised 5 September 2011; Accepted 19 September 2011

Academic Editor: Marco D. Santambrogio

Copyright © 2012 Angelo Kuti Lusala and Jean-Didier Legat. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Linked References

  1. G. De Micheli and L. Benini, Networks On Chips: Technology and Tools, Morgan Kaufman, 2006.
  2. M. A. A. Faruque and J. Henkel, “QoS-supported on-chip communication for multi-processors,” International Journal of Parallel Programming, vol. 36, no. 1, pp. 114–139, 2008. View at Publisher · View at Google Scholar
  3. E. Bolotin, I. Cidon, R. Ginosar, and A. Kolodny, “QNoC: QoS architecture and design process for network on chip,” Journal of Systems Architecture, vol. 50, no. 2-3, pp. 105–128, 2004. View at Publisher · View at Google Scholar
  4. N. Kavaldjiev, G. J. M. Smit, P. G. Jansen, and P. T. Wolkotte, “A virtual channel network-on-chip for GT and BE traffic,” in Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures, pp. 211–216, March 2006. View at Publisher · View at Google Scholar
  5. K. Goossens, J. Dielissen, and A. Radulescu, “ÆTHEREAL network-on-chip concepts,” IEEE Design and Test of computers, vol. 22, no. 5, pp. 414–421, 2005. View at Google Scholar
  6. S. Bourduas and Z. Zilic, “A hybrid ring/mesh interconnect for network-on-chip using hierarchical rings for global routing,” in Proceedings of the 1st International Symposium on Networks-on-Chip (NOCS '07), pp. 195–202, May 2007. View at Publisher · View at Google Scholar
  7. N. E. Jerger, M. Lipasti, and L. S. Peh, “Circuit-switched coherence,” IEEE Computer Architecture Letters, vol. 6, no. 1, pp. 5–8, 2007. View at Publisher · View at Google Scholar
  8. M. Modarressi, H. Sarbazi-Azad, and M. Arjomand, “A hybrid packet-circuit switched on-chip network based on SDM,” in Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE '09), pp. 566–569, April 2009.
  9. A. Leroy, P. Marchal, A. Shickova, F. Catthoor, F. Robert, and D. Verkest, “Spatial division multiplexing: a novel approach for guaranteed throughput on NoCs,” in Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and Systems Synthesis (CODES+ISSS '05), pp. 81–86, September 2005.
  10. A. K. Lusala and J.-D. Legat, “A hybrid router combining SDM-based circuit switching with packet switching for On-Chip networks,” in Proceedings of the International conference on Reconfigurable Computing and FPGAs (ReConFig '10), pp. 340–345, Quintano Roo, Mexico, December 2010.