An Evaluation of an Integrated On-Chip/Off-Chip Network for
High-Performance Reconfigurable Computing

<table>Block diagram of the hardware implementation of <span style="font-family:monospace">MPI_Reduce</span>.</table>

International Journal of Reconfigurable Computing

Figure 10: An Evaluation of an Integrated On-Chip/Off-Chip Network for
High-Performance Reconfigurable Computing 