An Evaluation of an Integrated On-Chip/Off-Chip Network for High-Performance Reconfigurable Computing

Table 3

Hardware send/receive latency through one hop.

Sender/receiver pair	Latency (𝜇s)
hw-to-hw (on chip)	0.02
hw-to-hw (off chip)	0.80
sw-to-hw (on chip)	0.15
sw-to-hw (off chip)	0.98
sw-to-sw (off chip)	2.00