Table of Contents Author Guidelines Submit a Manuscript
International Journal of Reconfigurable Computing
Volume 2012 (2012), Article ID 832531, 17 pages
http://dx.doi.org/10.1155/2012/832531
Research Article

HoneyComb: An Application-Driven Online Adaptive Reconfigurable Hardware Architecture

Institut für Technik der Informationsverarbeitung, Karlsruher Institut für Technologie (KIT), Engesserstraȣe 5, 76131 Karlsruhe, Germany

Received 21 February 2012; Accepted 24 May 2012

Academic Editor: Elmar Melcher

Copyright © 2012 Alexander Thomas et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Linked References

  1. Xilinx Inc., http://www.xilinx.com/.
  2. Altera Corp, http://www.altera.com/.
  3. J. Becker, T. Pionteck, and M. Glesner, “DReAM: a dynamically reconfigurable architecture for future mobile communication applications,” in Proceedings of the 10th International Conference on Field Programmable Logic and Applications, Villach, Austria, 2000.
  4. R. Kress, A fast reconfigurable ALU for Xputers [Ph.D. dissertation], Kaiserslautern University, 1996.
  5. T. Oppold, T. Schweizer, J. F. Oliveira, S. Eisenhardt, and W. Rosenstiel, “CRC—concepts and evaluation of processor-like reconfigurable archtitectures,” IT-Information Technology, vol. 49, no. 3, p. 147, 2007. View at Google Scholar
  6. A. Abnous, H. Zhang, M. Wan, G. Varghese, V. Prabhu, and J. Rabaey, “The Pleiades Architecture,” in The Application of Programmable DSPs in Mobile Communications, John Wiley & Sons, Chichester, UK, 2002. View at Google Scholar
  7. P. Master, “The next big leap in reconfigurable systems,” in IEEE International Conference on Field-Programmable Technology (FPT '02), pp. 17–22, December 2002.
  8. E. Schüler and M. Weinhardt, “XPP-III: the XPP-III reconfigurable processor core,” Lecture Notes in Electrical Engineering, vol. 40, pp. 63–76, 2009. View at Publisher · View at Google Scholar · View at Scopus
  9. N. Suzuki, S. Kurotaki, M. Suzuki et al., “Implementing and evaluating stream applications on the dynamically reconfigurable processor,” in Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '04), pp. 328–329, April 2004. View at Publisher · View at Google Scholar · View at Scopus
  10. P. M. Heysters, G. J. M. Smit, and E. Molenkamp, “Energy-efficiency of the MONTIUM reconfigurable tile processor,” in Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA '04), pp. 38–44, Las Vegas, Nev, USA, June 2004. View at Scopus
  11. S. C. Goldstein, H. Schmit, M. Budiu, S. Cadambi, M. Matt, and R. R. Taylor, “PipeRench: a reconfigurable architecture and compiler,” Computer, vol. 33, no. 4, pp. 70–77, 2000. View at Publisher · View at Google Scholar · View at Scopus
  12. D. C. Chen and J. M. Rabaey, “A reconfigurable multiprocessor IC for rapid prototyping of algorithmic-specific high-speed DSP data paths,” IEEE Journal of Solid-State Circuits, vol. 27, no. 12, pp. 1895–1904, 1992. View at Publisher · View at Google Scholar · View at Scopus
  13. C. Ebeling, C. Fisher, G. Xing, M. Shen, and H. Liu, “Implementing an OFDM receiver on the RaPiD reconfigurable architecture,” IEEE Transactions on Computers, vol. 53, no. 11, pp. 1436–1448, 2004. View at Publisher · View at Google Scholar · View at Scopus
  14. G. Lu, H. Singh, M.-H. Lee et al., “The MorphoSys dynamically reconfigurable system-on-chip,” in Proceedings of the 1st NASA/DoD Workshop on Evolvable Hardware, pp. 152–160, 1999.
  15. E. Mirsky and A. DeHon, “MATRIX: a reconfigurable computing architecture with configurable instruction distribution and deployable resources,” in Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, pp. 157–166, April 1996. View at Scopus
  16. T. Miyamori and U. Olukotun, “A quantitative analysis of reconfigurable coprocessors for multimedia applications,” in Proceedings of IEEE Symposium on FPGAs for Custom Computing Machines, pp. 2–11, April 1998.
  17. A. Thomas and J. Becker, “New adaptive multi-grained hardware architecture for processing of dynamic function patterns (Neue adaptive multi-granulare Hardwarearchitektur),” IT-Information Technology, vol. 49, no. 3, p. 165, 2007. View at Google Scholar
  18. A. Thomas and J. Becker, “Multi-grained reconfigurable hardware architecture with online-adaptive routing techniques,” in Proceedings of the IFIP International Conference on Very Large Scale Integration (IFIP VLSI-SOC '05), Perth, Western Australia, October 2005.
  19. P. Briggs, Register Allocation via Graph Coloring, Rice University, Dissertation, 1992.
  20. C. J. Tseng and D. P. Siewiorek, “Automated synthesis of data paths in digital systems,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 5, no. 3, pp. 379–395, 1986. View at Google Scholar · View at Scopus
  21. VMEbus International Trade Association (VITA)—FMC Marketing Alliance, http://www.vita.com/fmc.html.
  22. E. O. Brigham and R. E. Morrow, “The fast Fourier transform,” IEEE Spectrum, vol. 4, no. 12, pp. 63–70, 1967. View at Google Scholar
  23. St. Mallat, Phane: A Wavelet Tour of Signal Processing, Academic Press, 2009.
  24. V. Nikolajevic and G. Fettweis, “New recursive algorithms for the unified forward and inverse MDCT/MDST,” Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, vol. 34, no. 3, pp. 203–208, 2003. View at Publisher · View at Google Scholar · View at Scopus
  25. J. Daemen and V. Rijmen, “AES proposal: Rijndael,” 1999.
  26. W. J. Cooley and W. J. Tukey, “An algorithm for the machine calculation of complex Fourier series,” Mathematics of Computation, vol. 19, pp. 297–301, 1965. View at Publisher · View at Google Scholar
  27. National Institute of Standards and Technology, http://www.nist.gov/index.html.