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International Journal of Reconfigurable Computing
Volume 2012, Article ID 915178, 12 pages
Research Article

NCOR: An FPGA-Friendly Nonblocking Data Cache for Soft Processors with Runahead Execution

Department of Electrical and Computer Engineering, University of Toronto, Toronto, ON, Canada

Received 30 April 2011; Revised 22 August 2011; Accepted 27 August 2011

Academic Editor: Viktor K. Prasanna

Copyright © 2012 Kaveh Aasaraai and Andreas Moshovos. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Linked References

  1. K. Aasaraai and A. Moshovos, “Towards a viable out-of-order soft core: copy-free, checkpointed register renaming,” in the 19th International Conference on Field Programmable Logic and Applications (FPL '09), Prague, Czech Republic, September 2009.
  2. J. Dundas and T. Mudge, “Improving data cache performance by pre-executing instructions under a cache miss,” in Proceedings of the International Conference on Supercomputing, pp. 68–75, July 1997. View at Scopus
  3. K. Aasaraai and A. Moshovos, “An efficient non-blocking data cache for soft processors,” in Proceedings of the International Conference on ReConFigurable Computing and FPGAs, December 2010.
  4. D. Kroft, “Lockup-free instruction fetch/prefetch cache organization,” in Proceedings of the 8th Annual International Symposium on Computer Architecture, pp. 81–87, 1982. View at Scopus
  5. Altera Corp., “Nios II Processor Reference Handbook v10.0,” 2010.
  6. Altera Corp, “Stratix III Device Handbook: Chapter 4. TriMatrix Embedded Memory Blocks in Stratix III Devices,” 2010.
  7. Arcturus Networks Inc, “uClinux,”
  8. Standard Performance Evaluation Corporation, “SPEC CPU 2006,”
  9. P. Yiannacouras and J. Rose, “A parameterized automatic cache generator for FPGAs,” in Proceedings of Field-Programmable Technology (FPT), pp. 324–327, 2003.
  10. IBM and LSI, “PowerPC 476FP Embedded Processor Core and PowerPC 470S Synthesizable Core User's Manual,”
  11. G. Stitt and J. Coole, “Traversal caches: a framework for FPGA acceleration of pointer data structures,” International Journal of Reconfigurable Computing, vol. 2010, Article ID 652620, 16 pages, 2010. View at Publisher · View at Google Scholar