NCOR: An FPGA-Friendly Nonblocking Data Cache for Soft Processors with Runahead Execution

Table 1

Architectural properties of simulated processors.

I-cache size (Bytes)	32 K
D-Cache size (Bytes)	4–32 K
Cache line size	32 bytes
Cache associativity	Direct mapped
Memory latency	26 cycles
BPredictor type	GShare
BPredictor entries	4096
BTB entries	256
Pipeline stages	5
No. of outstanding misses	32