International Journal of Reconfigurable Computing / 2013 / Article / Fig 15

Research Article

Transparent Runtime Migration of Loop-Based Traces of Processor Instructions to Reconfigurable Processing Units

Figure 15

FPGA resources, synthesis frequency, and required configuration bits for each RPU with a PLB interface (LUTs and FFs shown on the left axis).
340316.fig.0015

We are committed to sharing findings related to COVID-19 as quickly as possible. We will be providing unlimited waivers of publication charges for accepted research articles as well as case reports and case series related to COVID-19. Review articles are excluded from this waiver policy. Sign up here as a reviewer to help fast-track new submissions.