Transparent Runtime Migration of Loop-Based Traces of Processor Instructions to Reconfigurable Processing Units

Figure 16

Speedups for all three architectures. Results for DDR-PLB architecture (Arch. 1) use the axis on the right. Bar labels show the results for the LMB-PLB (Arch. 2) and LMB-FSL (Arch. 3) architectures (axis on the left). The maximum possible speedups (dotted line relative to the left axis) are estimations calculated using (1), assuming an instruction fetch latency of 1 cycle. A trend can be observed for all three cases. The different overheads dictate the relative scales of the attained speedups.