Research Article
Analysis of Fast Radix-10 Digit Recurrence Algorithms for Fixed-Point and Floating-Point Dividers on FPGAs
Table 7
Postplace and route result of a 64-bit binary floating-point divider (Core Gen).
| ߙ | Cycles per division | 1 | 10 | 20 | 55 |
| No. of LUTs | 3161 | 592 | 425 | 394 | No. of FFs | 196 | 518 | 469 | 542 | No. of LUTs and FFs comb. | 3232 | 917 | 675 | 675 | Cycle time (ns) | 153.7 | 20.8 | 8.9 | 6.8 | Overall latency (ns) | 153.7 | 208 | 178 | 374 | Max. frequency (MHz) | 6.5 | 48 | 112 | 147 |
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