An Asynchronous FPGA Block with Its Tech-Mapping Algorithm Dedicated to Security Applications

<div class="floats-full-page floats-full-page-figure"><h2>Figure 9</h2><div class="floats-full-page-caption"><table>Three-state encoding.</table></div><div class="floats-full-page-content"><table class="table-group" width="800px"><tr class="fig-image"><td><img alt="517947.fig.009" src="https://static-01.hindawi.com/articles/ijrc/volume-2013/517947/figures/517947.fig.009.jpg" /></td></tr></table></div></div>

Figure 9 | An Asynchronous FPGA Block with Its Tech-Mapping Algorithm Dedicated to Security Applications

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Figure 9: An Asynchronous FPGA Block with Its Tech-Mapping Algorithm Dedicated to Security Applications

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Figure 9

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<p><em>International Journal of Reconfigurable Computing</em> aims to serve the large community of researchers and professional engineers working on the theoretical and practical aspects of reconfigurable computing.</p>


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