Table of Contents Author Guidelines Submit a Manuscript
International Journal of Reconfigurable Computing
Volume 2013, Article ID 783501, 10 pages
http://dx.doi.org/10.1155/2013/783501
Research Article

Development of a SoC for Digital Television Set-Top Box: Architecture and System Integration Issues

PGMICRO, UFRGS, Avenida Bento Gonçalves 9500, 91501-970 Porto Alegre, RS, Brazil

Received 21 January 2012; Revised 14 November 2012; Accepted 16 December 2012

Academic Editor: Oliver Sander

Copyright © 2013 André Borin Soares et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Linked References

  1. K. Yang, C. Zhang, G. Du, J. Xie, and Z. Wang, “A hardware-software co-design for H.264/AVC decoder,” in Proceedings of the IEEE Asian Solid-State Circuits Conference (ASSCC '06), pp. 119–122, Beijing, China, November 2006. View at Publisher · View at Google Scholar · View at Scopus
  2. “ITU-T recommendation H. 264: advanced video coding for generic audiovisual services,” Video Coding Experts Group, 2005.
  3. JEDEC, JESD79-2F: DDR2 SDRAM Specification, JEDEC Solid State Technology Association, Arlington, Va, USA, 2009.
  4. F. Pescador, G. Maturana, M. J. Garrido, E. Juarez, and C. Sanz, “An H.264 video decoder based on a DM6437 DSP,” in Proceedings of the International Conference on Consumer Electronics (ICCE '09), Las Vegas, Nev, USA, January 2009. View at Publisher · View at Google Scholar · View at Scopus
  5. C. C. Lin, J. W. Chen, H. C. Chang et al., “A 160K gates/4.5 KB SRAM H.264 video decoder for HDTV applications,” IEEE Journal of Solid-State Circuits, vol. 42, no. 1, pp. 170–181, 2007. View at Publisher · View at Google Scholar · View at Scopus
  6. ST SPEAr 1340 dual-core cortex A9 HMI embedded MPU, http://www.st.com/.
  7. A. C. Bonatto, A. B. Soares, A. Renner, A. A. Susin, L. M. Silva, and S. Bampi, “A 720p H.264/AVC decoder ASIC implementation for digital television set-top boxes,” in Proceedings of the 23rd Symposium on Integrated Circuits and Systems Design (SBCCI '10), pp. 168–173, September 2010. View at Publisher · View at Google Scholar · View at Scopus
  8. ABNT, NBR15602 Digital Terrestrial Television—Video Coding, Audio Coding and Multiplexing, ABNT, 2007.
  9. “Project Rede H. 264,” http://www.lapsi.eletro.ufrgs.br/h264/wiki/tiki-index.php.
  10. “Project SoC-SBTVD,” http://www.lapsi.eletro.ufrgs.br/soc-sbtvd/wiki/tiki-index.php/.
  11. ABNT, “NBR15604 digital terrestrial television—receivers,” ABNT, 2007.
  12. “Gaisler research Leon3 processor,” http://www.gaisler.com/.
  13. M. Horowitz, A. Joch, F. Kossentini, and A. Hallapuro, “H.264/AVC baseline profile decoder complexity analysis,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 13, no. 7, pp. 704–716, 2003. View at Publisher · View at Google Scholar · View at Scopus
  14. A. Renner and A. Susin, “An MPEG-4 AAC decoder FPGA implementation for the Brazilian Digital Television,” in Proceedings of the 8th Southern Conference on Programmable Logic (SPL '12), pp. 1–6, Bento Gonçalves, Brasil, March 2012.
  15. P. Van Der Wolf and T. Henriksson, “Video processing requirements on SoC infrastructures,” in Proceedings of the Design, Automation and Test in Europe (DATE '08), pp. 1124–1125, ACM, Munich, Germany, March 2008. View at Publisher · View at Google Scholar · View at Scopus
  16. C. H. Li, C. H. Chang, W. H. Peng, W. Hwang, and T. Chiang, “Design of memory sub-system in H.264/AVC decoder,” in Proceedings of the Digest of Technical Papers International Conference on Consumer Electronics (ICCE '07), pp. 1–2, January 2007. View at Publisher · View at Google Scholar · View at Scopus
  17. Xilinx, http://www.xilinx.com/.
  18. A. C. Bonatto, A. B. Soares, and A. A. Susin, “Multichannel SDRAM controller design for H.264/AVC video decoder,” in Proceedings of the 7th Southern Conference on Programmable Logic (SPL '11), pp. 137–142, Córdoba, Argentina, April 2011. View at Publisher · View at Google Scholar · View at Scopus
  19. B. Zatt, A. Azevedo, L. Agostini, A. Susin, and S. Bampi, “Memory hierarchy targeting bi-predictive motion compensation for H.264/AVC decoder,” in Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07), pp. 445–446, Porto Alegre, Brazil, March 2007. View at Publisher · View at Google Scholar · View at Scopus
  20. “H.S. Coordination,” JM Software, http://iphome.hhi.de/suehring/tml.
  21. A. B. Soares, A. Bonatto, and A. Susin, “Integration issues on the development of an H.264/AVC video decoder SoC for SBTVD set top box,” in Proceedings of the 24th Symposium on Integrated Circuits and Systems Design (SBCCI '11), August-September 2011.