Impact of Dual Placement and Routing on WDDL Netlist Security in FPGA

<table>Adjacent partitioning steps in multilevel architecture <svg height="10.9125" id="M96" style="vertical-align:-0.0pt" version="1.1" viewbox="0 0 59.674999 10.9125" width="59.674999" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink">
<g transform="matrix(.017,-0,0,-.017,.062,10.862)"><path d="M456 178h-96v-72q0 -51 12.5 -62.5t72.5 -16.5v-27h-256v27q65 5 78 17t13 62v72h-260v28q182 271 300 426h40v-407h96v-47zM280 225v295h-2q-107 -148 -196 -295h198z" id="x34"></path></g><g transform="matrix(.017,-0,0,-.017,11.996,10.862)"><path d="M528 54l-36 -38l-198 201l-198 -201l-36 38l197 200l-197 201l36 38l198 -202l198 202l36 -38l-197 -201z" id="xD7"></path></g><g transform="matrix(.017,-0,0,-.017,25.748,10.862)"><path d="M412 140l28 -9q0 -2 -35 -131h-373v23q112 112 161 170q59 70 92 127t33 115q0 63 -31 98t-86 35q-75 0 -137 -93l-22 20l57 81q55 59 135 59q69 0 118.5 -46.5t49.5 -122.5q0 -62 -29.5 -114t-102.5 -130l-141 -149h186q42 0 58.5 10.5t38.5 56.5z" id="x32"></path></g><g transform="matrix(.017,-0,0,-.017,37.681,10.862)"><path d="M528 54l-36 -38l-198 201l-198 -201l-36 38l197 200l-197 201l36 38l198 -202l198 202l36 -38l-197 -201z" id="xD7"></path></g><g transform="matrix(.017,-0,0,-.017,51.433,10.862)"><path d="M456 178h-96v-72q0 -51 12.5 -62.5t72.5 -16.5v-27h-256v27q65 5 78 17t13 62v72h-260v28q182 271 300 426h40v-407h96v-47zM280 225v295h-2q-107 -148 -196 -295h198z" id="x34"></path></g>
</svg>.</table>

International Journal of Reconfigurable Computing

fig14

Figure 14

Figure 14: Impact of Dual Placement and Routing on WDDL Netlist Security in FPGA 