Impact of Dual Placement and Routing on WDDL Netlist Security in FPGA

Table 10

Impact of cluster size on critical path delay.

WDDL; benchs	Differential pair routing						Routability-driven routing
	𝑁=2 LBs		𝑁=4 LBs		𝑁=8 LBs		𝑁=2 LBs		𝑁=4 LBs		𝑁=8 LBs
	Critical; Sw. Nb.	Critical; delay (ns)	Critical; Sw. Nb.	Critical; delay (ns)	Critical; Sw. Nb.	Critical; delay (ns)	Critical; Sw. Nb.	Critical; delay (ns)	Critical; Sw. Nb.	Critical; delay (ns)	Critical; Sw. Nb.	Critical; delay (ns)
DES	147	16.52	154	16.78	106	18.18	149	16.23	139	14.58	92	16.86
BarreI16	102	10.8	98	13.67	82	14.06	85	9.43	118	14	72	12.42
BarreI32	175	20.32	167	22.37	103	20.47	176	18.32	176	21.52	106	20.7
BarreI64	211	23.7	233	32.0	121	24.8	232	26.64	228	27.8	153	29.39
Mux8	96	9.07	79	9.45	74	12.54	194	18	107	11.18	90	15.64
Mux32	133	13.11	116	14.0	94	16.17	150	14	131	14.15	112	18.62
xbar_16×16	73	7.04	52	6.79	51	9.56	84	8.25	53	6.53	58	9.95
Average	133	14.36	128	16.43	90	16.53	152	14.41	136	15.71	97	17.52