Impact of Dual Placement and Routing on WDDL Netlist Security in FPGA

Table 2

Placement results (Δ𝑑𝑒𝑙𝑎𝑦) of WDDL netlists in mesh FPGA.

WDDL; design	Nets	Unconstrained placement				Symmetrical placement				Adjacent placement
		Max; (ps)	Mean; (ps)	Std. Dev.; (ps)	Switch; mismatch	Max; (ps)	Mean; (ps)	Std. Dev.; (ps)	Switch; mismatch	Max; (ps)	Mean; (ps)	Std. Dev.; (ps)	Switch; mismatch
DES	2162	5317	607	746	2375	4623	289	551	1431	1989	121	176	1476
BarreI16	628	2323	458	466	815	1480	164	229	532	2448	165	299	479
BarreI32	1482	6825	829	908	2072	5504	333	648	1266	5140	222	440	1247
BarreI64	3254	8351	1114	1229	4760	10330	674	1269	3158	7090	252	545	2841
Mux8_64 bit	2988	7023	579	939	2242	6263	230	645	676	2960	76	255	553
Mux32_16 bit	3072	3683	447	536	2301	4271	108	353	630	1702	58	147	620
xbar_16×16	706	5745	634	850	732	3706	258	375	485	3013	92	195	384
Average	2041	5752	666	810	2185	5168	293	581	1168	3477	140	293	1085