Impact of Dual Placement and Routing on WDDL Netlist Security in FPGA

Table 3

Placement results (Δ𝑑𝑒𝑙𝑎𝑦) of WDDL netlists in MFPGA.

WDDL; design	Unconstrained placement				Symmetrical placement				Adjacent placement
	Max; (ps)	Mean; (ps)	Std. Dev.; (ps)	Switch; mismatch	Max; (ps)	Mean; (ps)	Std. Dev.; (ps)	Switch; mismatch	Max; (ps)	Mean; (ps)	Std. Dev.; (ps)	Switch; mismatch
DES	7006	1420	1438	1131	6840	732	870	110	4106	365	429	34
BarreI16	3828	648	660	242	2505	375	312	21	1946	231	235	11
BarreI32	5317	1165	1094	961	3631	420	468	104	3054	330	426	90
BarreI64	9157	1664	1752	1368	7000	1128	933	145	6902	542	636	96
Mux8_64 bit	8940	2004	2205	1088	6303	813	843	79	5385	386	539	25
Mux32_16 bit	8834	1882	2056	956	6742	849	869	82	6458	401	560	34
xbar_16×16	3281	724	672	272	2258	347	249	8	1344	137	139	2
Average	6622	1358	1411	859	5039	666	649	78	4170	341	423	41