Impact of Dual Placement and Routing on WDDL Netlist Security in FPGA

Table 4

Timing-balance-driven routing results (Δ𝑑𝑒𝑙𝑎𝑦) of WDDL designs in MFPGA.

WDDL; designs	Max; (ps)	Mean; (ps)	Std. Dev.; (ps)	Sw. Mis.; Signals	Total; Diff_sw_nb	Routability_driven; critical path delay (ns)	Timing_balanced_driven; critical path delay (ns)
DES	571	85	92	0	0	56.62	51.55
BarreI16	395	50	55	0	0	24.04	21.14
BarreI32	921	70	75	0	0	21.23	18.52
BarreI64	1333	133	148	0	0	61.72	59.9
Mux8_64 bit	881	44	71	0	0	28.75	25.84
Mux32_16 bit	801	61	88	0	0	40.11	37.82
xbar_16×16	366	32	55	0	0	13.39	13.84
Average	752	67	69	0	0	35.12	32.65