Impact of Dual Placement and Routing on WDDL Netlist Security in FPGA

Table 5

Timing-balance-driven routing results (Δ𝑑𝑒𝑙𝑎𝑦) of WDDL designs in simple mesh FPGA.

WDDL; designs	Max; (ps)	Mean; (ps)	Std. Dev.; (ps)	Sw. Mis.; signals	Total; Diff_sw_nb	Routability_driven; critical path delay (ns)	Timing_balanced_driven; critical path delay (ns)
DES	739	64	75	1419	2191	19.84	19.55
BarreI16	540	45	60	371	508	9.4	8.7
BarreI32	975	56	83	875	1432	8.32	8.59
BarreI64	1620	71	107	2198	3831	25.29	20.77
Mux8_64 bit	798	25	56	371	568	12.09	10.62
Mux32_16 bit	494	20	39	268	383	17.47	16.53
xbar_16×16	539	30	49	232	330	8.59	6.49
Average	815	44	67	819	1320	14.42	13.03