Impact of Dual Placement and Routing on WDDL Netlist Security in FPGA

Table 6

Timing-balance-driven routing results (Δ𝑑𝑒𝑙𝑎𝑦) of WDDL designs in cluster-based mesh FPGA (2 LBs).

WDDL; designs	Adjacent placement and routability-driven routing						Adjacent placement and timing-balance-driven routing
	Max; (ps)	Mean; (ps)	Std. Dev.; (ps)	Sw. Mis.; Signals	Total; Diff_sw_nb	Critical; path delay (ns)	Max; (ps)	Mean; (ps)	Std. Dev.; (ps)	Sw. Mis.; Signals	Total; Diff_sw_nb	Critical; path delay (ns)
DES	2383	107	218	1099	3209	16.23	813	34	70	631	990	15.66
BarreI16	2400	260	364	604	2757	9.43	620	91	102	536	977	9.2
BarreI32	4810	463	770	1455	10654	18.32	1616	117	158	1351	2824	16.2
BarreI64	8926	646	1093	3391	32299	26.64	2131	149	197	3190	7759	23.96
Mux8_64 bit	5751	464	781	1706	14421	11.58	1899	61	132	894	1940	9.94
Mux32_16 bit	4505	159	451	852	4936	14.02	1376	46	95	846	1445	14.07
xbar_16×16	3245	182	375	423	1863	8.25	621	58	82	355	581	6.32
Average	4574	325	578	136	10023	14.92	1296	79	119	1114	2359	13.62