Impact of Dual Placement and Routing on WDDL Netlist Security in FPGA

Table 7

Characteristics of simple mesh, cluster-based mesh and MFPGA architectures with timing-balance-driven routing.

WDDL; benchs	MFPGA			Simple mesh				Cluster-based mesh (𝑁=2 LBs)
	Architecture; levels	SW; ×10^3	Area; ×10^6𝜆^2	𝑁×𝑁	Channel; width	SW; ×10^3	Area; ×10^6𝜆^2	𝑁×𝑁	Channel; width	SW; ×10^3	Area; ×10^6𝜆^2
DES	6×8×8×8	506	1499	47×47	20	625	1797	33×33	16	474	1354
BarreI16	6×6×6×6	177	526	25×25	18	160	465	18×18	16	141	405
BarreI32	4×8×8×8	380	1089	38×38	24	492	1387	27×27	22	415	1156
BarreI64	8×8×8×8	786	2268	56×56	32	1418	3914	40×40	24	980	2705
Mux8	8×8×8×8	729	2132	55×55	32	1368	3776	39×39	12	526	1559
Mux32	6×8×8×8	729	2139	54×54	24	989	2794	38×38	14	564	1638
xbar	6×6×6×6	203	587	24×24	12	102	304	17×17	12	102	301
Average		501	1462			736	2062		16	457	1302