Impact of Dual Placement and Routing on WDDL Netlist Security in FPGA

Table 9

Cluster-based mesh architecture characteristics for different cluster sizes.

WDDL; benchs	Differential pair routing
	𝑁=2 LBs				𝑁=4 LBs				𝑁=8 LBs
	𝑁×𝑁	Channel; width	SW; ×10^3	Area; ×10^6𝜆^2	𝑁×𝑁	Channel; width	SW; ×10^3	Area; ×10^6𝜆^2	𝑁×𝑁	Channel; width	SW; ×10^3	Area; ×10^6𝜆^2
DES	33×33	18	522	1486	24×24	20	625	1742	17×17	28	938	2460
BarreI16	18×18	16	141	405	13×13	28	236	638	10×10	28	325	851
BarreI32	27×27	24	447	1236	19×19	26	475	1296	14×14	40	802	2076
BarreI64	40×40	26	1051	2879	28×28	30	1150	3104	20×20	44	1749	4505
Mux8	39×39	12	526	1559	28×28	16	730	2058	20×20	28	1299	3405
Mux32	38×38	14	564	1638	27×27	20	791	2204	19×19	32	1274	3318
xbar_16×16	17×17	12	102	301	12×12	18	145	412	9×9	32	286	744
Average		18	479	1357		22	593	1636		34	961	2479