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International Journal of Reconfigurable Computing
Volume 2014 (2014), Article ID 243835, 9 pages
Research Article

Scalable Fixed Point QRD Core Using Dynamic Partial Reconfiguration

Department of Avionics, IIST, Thiruvananthapuram 695547, India

Received 15 August 2014; Revised 16 November 2014; Accepted 20 November 2014; Published 14 December 2014

Academic Editor: Neil Bergmann

Copyright © 2014 Gayathri R. Prabhu et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


A Givens rotation based scalable QRD core which utilizes an efficient pipelined and unfolded 2D multiply and accumulate (MAC) based systolic array architecture with dynamic partial reconfiguration (DPR) capability is proposed. The square root and inverse square root operations in the Givens rotation algorithm are handled using a modified look-up table (LUT) based Newton-Raphson method, thereby reducing the area by 71% and latency by 50% while operating at a frequency 49% higher than the existing boundary cell architectures. The proposed architecture is implemented on Xilinx Virtex-6 FPGA for any real matrices of size , where and by dynamically inserting or removing the partial modules. The evaluation results demonstrate a significant reduction in latency, area, and power as compared to other existing architectures. The functionality of the proposed core is evaluated for a variable length adaptive equalizer.