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International Journal of Reconfigurable Computing
Volume 2014, Article ID 495080, 7 pages
Research Article

An FPGA Task Placement Algorithm Using Reflected Binary Gray Space Filling Curve

1Department of Electronics and Communication Engineering, Sri Krishna College of Technology, Coimbatore, Tamilnadu 641042, India
2Department of Computer Science Engineering, Government College of Technology, Coimbatore, Tamilnadu 641013, India

Received 30 September 2013; Revised 30 December 2013; Accepted 24 January 2014; Published 16 April 2014

Academic Editor: Koen L. M. Bertels

Copyright © 2014 Senoj Joseph Olakkenghil and K. Baskaran. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


With the arrival of partial reconfiguration technology, modern FPGAs support tasks that can be loaded in (removed from) the FPGA individually without interrupting other tasks already running on the same FPGA. Many online task placement algorithms designed for such partially reconfigurable systems have been proposed to provide efficient and fast task placement. A new approach for online placement of modules on reconfigurable devices, by managing the free space using a run-length based representation. This representation allows the algorithm to insert or delete tasks quickly and also to calculate the fragmentation easily. In the proposed FPGA model, the CLBs are numbered according to reflected binary gray space filling curve model. The search algorithm will quickly identify a placement for the incoming task based on first fit mode or a fragmentation aware best fit mode. Simulation experiments indicate that the proposed techniques result in a low ratio of task rejection and high FPGA utilization compared to existing techniques.