Architecture and Application-Aware Management of Complexity of Mapping Multiplication to FPGA DSP Blocks in High Level Synthesis

Table 10

Variation in LUT consumption for different 9-bit constants with the same number of 1′s in binary representation.

Constant	Binary	Number of 1′s	LUT	CLK (ns)	Number of FAs
260	100000100	2	9	2.077	9
259	100000011	3	16	2.509	22
261	100000101	3	15	2.479	21
383	101111111	8	63,47	5.490	62
447	110111111	8	63,48	5.638	62
479	111011111	8	62,50	5.781	62
495	111101111	8	64,51	5.855	64
503	111110111	8	61,50	5.556	63
510	111111110	8	56,45	5.687	62
511	111111111	9	60,49	5.501	70