Hardware-Efficient Design of Real-Time Profile Shape Matching Stereo Vision Algorithm on FPGA

Table 2

FPGA logic utilized by the profile shape matching hardware design capable of processing images as large as the Teddy and Cones images (450 × 375, 60 disp) on a Xilinx Virtex 4 FX60.

Logic	Used	Available	Utilization
Total number of slice registers	6,314	50,560	12.5%
Number of 4 input LUTs	9,637	50,560	19%
Number of RAMB 16 s	30	232	13%
Number of DSP 48 s	20	128	16%